Ab­stract

We pre­sent a method­ol­ogy for au­to­matic syn­the­sis of power man­age­ment con­trollers for Sys­tem-on-Chip de­signs by using an ex­tended ver­sion of the Uni­fied Power For­mat (UPF). Our method­ol­ogy takes an SoC de­sign and a UPF-based power de­sign, and au­to­mat­i­cally gen­er­ates a power man­age­ment con­troller in Ver­ilog/VHDL that im­ple­ments the power state ma­chine spec­i­fied in UPF. It per­forms a pri­or­ity-based sched­ul­ing for all power state ma­chine ac­tions, con­nects each power man­age­ment sig­nal to the cor­re­spond­ing logic wire in the UPF de­sign and in­te­grates the con­troller into the Sys­tem-on-Chip using a con­fig­urable bus in­ter­face. We im­ple­mented the pro­posed ap­proach as a plu­gin for Syn­op­sys De­sign Com­piler to close the gap in today’s power man­age­ment flows and eval­u­ated it by a RISC-V Sys­tem-on-Chip.